1. Field of the Invention
The present invention relates to electronic assemblies and further to electronic component attachment to a substrate in the manufacture of such assemblies. More particularly, the present invention relates to chip attachment, such as, flip chip joining to a substrate.
2. Background and Related Art
Typical conventional processes for joining a chip to a substrate involve applying flux to the substrate at the chip site and placing the chip with solder bumps on the substrate at such site. Heat is then applied such that the flux reacts with the joining pads on the substrate and, thereafter, the solder bumps on the chip melt in the presence of the flux thereby joining the chip to the substrate joining pads. Typical of such processes is that known as the C-4 process.
Variations of such processes are also known. For example, various pretreatment and post-treatment steps may be employed. Typical of the pretreatment steps are those used to pretreat the substrate surface with a plasma. Such steps may be necessary, for example, to make organic substrates, such as laminates, more wettable. Such steps may be undertaken to alleviate problems, such as, adhesion of underfill after the chip joining operation.
However, it has been found that organic laminate substrates, particularly plasma pretreated laminate substrates, tended to result in more frequent improper joining of the chip solder bumps to the substrate joining pads. Although initially the cause of such improper joining was unclear, it has been discovered that excessive spreading of the flux caused a lack of flux where needed at the joining pads. Applying more flux to the chip site on the substrate tends to create other problems, such as, the floating and movement of the chip.
Thus, one of the difficulties with laminate surfaces, and particularly those that have been plasma pretreated, is that their wettable surface characteristics create conditions which result in excessive flux spreading. Excessive flux spreading, in turn, reduces the amount of flux at the chip site necessary to make good electrical connection upon solder reflow during chip attachment.
It is known in the art to use various forms of bulk barriers and dams which act to inhibit, at various points in the process, the spreading of various fabricating materials, such as, epoxy underfills and encapsulating materials. Often, such barriers are relatively viscous materials of such bulk so as to prevent the flow of the material to be controlled. It is also known to use low wetting dams to confine materials, such as, solder paste or surface bonding material.
Such techniques, however, can be cumbersome and costly to carry out. For example, use of such techniques typically requires removal of the dam material after processing. Where dams are not removed, their presence may interfere with subsequent operations. Moreover, application of the dam material is difficult to control, and limited space on the substrate surface may prohibit their effective use. In addition, such known processes and techniques most often do not have general utility but are limited in their application to the specific problem solved thereby.